1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same in which formation of a semiconductor having a induction element formed above a semiconductor substrate, such as a silicon wafer is done together with packaging thereof.
Priority is claimed on Japanese Patent Application No. 2004-221785, filed Jul. 29, 2004, and Japanese Patent Application No. 2004-302696, filed Oct. 18, 2004, the contents of which are incorporated herein by reference.
2. Description of Related Art
In recent years, in a fabrication of a high-frequency semiconductor element, an induction element, such as a spiral inductor, is formed on a semiconductor substrate for the purpose of ensuring impedance matching thereof or the like. In such a semiconductor element, however, a part of electromagnetic energy generated by the induction element is lost in the substrate or a wiring constructing the induction element due to parasitic capacitance between the wiring and the semiconductor substrate. This type of energy loss is disclosed in, for example, Japanese Unexamined Patent Application, First Publication No. 2003-86690.
One cause of this type of electromagnetic energy loss is a relatively close vertical distance between the wiring and the semiconductor substrate, which makes the influence of the parasitic capacitance significant. To eliminate such losses, one technique is proposed in which a thick resin layer is provided between the semiconductor substrate and the induction element so that loss of electromagnetic energy is prevented (see, for example, NIKKEI MICRODEVICES, March 2002, pp. 125-127).
FIGS. 1, 2A, and 2B illustrate an example of a conventional semiconductor device having a spiral coil. FIG. 1 is a plan view, FIG. 2A is a partially broken perspective view, and FIG. 2B is a cross-sectional view taken along line B-B shown in FIG. 1.
In a semiconductor device 20, a semiconductor substrate 1 includes an integrated circuit (IC) 2 formed thereon, and electrodes 3 and a passivation film 4 (insulator film) of the integrated circuit 2 are provided above the surface of the semiconductor substrate 1.
Furthermore, a lower wiring layer 21 that is connected to the electrodes 3 is formed on the passivation film 4 above the semiconductor substrate 1, and an insulating resin layer 22 is formed over the semiconductor substrate 1 and the lower wiring layer 21. Above the insulating resin layer 22, an upper wiring layer 23 having a spiral coil 24 is provided as a dielectric element. The spiral coil 24 is connected to the electrodes 3 of the integrated circuit 2 via the lower wiring layer 21.
FIGS. 3A to 3D are schematic cross-sectional views stepwise illustrating an exemplary method for manufacturing the semiconductor device shown in FIGS. 1, 2A, and 2B.
First, as shown in FIG. 3A, the semiconductor substrate 1 having the integrated circuit 2, the electrodes 3, and the passivation film 4 is provided. The semiconductor substrate 1 is, for example, a silicon wafer on which aluminum pads have been provided as the electrodes 3, which are covered with the passivation film 4 made of SiN, SiO2, or the like. In the passivation film 4, openings 5 are defined in the positions corresponding to the electrodes 3, and the electrodes 3 are exposed from the openings 5. The passivation film 4 may be formed, for example, using any well-known method, such as the low-pressure chemical vapor deposition (LPCVD) technique, to a thickness of between 0.1 μm and 0.5 μm, for example.
Next, as shown in FIG. 3B, the lower wiring layer 21 is formed on the passivation film 4 above the semiconductor substrate 1. The lower wiring layer 21 is a redistribution layer (under path) that connects between the electrodes 3 and the spiral coil 24, and first ends 21a thereof are connected to the electrodes 3, and second ends 21b are connected to ends 23a and 23b of the upper wiring layer 23 that are provided above the lower wiring layer 21 (see FIG. 3D). The material of the lower wiring layer 21 may be, aluminum or copper, for example, and the thickness thereof may be between 0.1 μm and 10 μm, for example. The lower wiring layer 21 may be formed using any well-known method, for example, sputtering, evaporation, plating, or the like.
Next, as shown in FIG. 3C, the insulating resin layer 22 is formed over the passivation film 4 and the lower wiring layer 21 above the semiconductor substrate 1. The insulating resin layer 22 may be made of, for example, a polyimide resin, an epoxy resin, a silicone resin, or the like, and the thickness thereof may be between 0.1 μm and 10 μm, for example. The insulating resin layer 22 may be formed using any well-known method, for example, the spin coating method, the printing method, the lamination method, or the like. In the insulating resin layer 22, the openings 25 are defined in the positions corresponding to the second ends 21b of the lower wiring layer 21 (two openings are shown in FIGS. 3A to 3D). The openings 25 may be defined using a patterning technique or the like, by means of photolithography, for example.
Next, as shown in FIG. 3D, the upper wiring layer 23 having the spiral coil 24 is formed on the insulating resin layer 22. The ends 23a and 23b of the upper wiring layer 23 penetrates through the openings 25 defined in the insulating resin layer 22 and are connected to the second ends 21b of the lower wiring layer 21 through the openings 25. The material of the upper wiring layer 23 may be, for example, copper, and the thickness thereof may be, for example, between 1 μm and 20 μm. The upper wiring layer 23 may be formed, for example, using any well-known technique, such as electroplating.
Although the spiral coil 24 is formed in the upper wiring layer 23 in the conventional example shown in FIGS. 3A to 3D, the spiral coil 24 may be formed on the lower wiring layer 21 as shown FIGS. 4A to 4D. Next, a procedure for manufacturing a semiconductor device in which the spiral coil 24 is formed in the lower wiring layer 21 will be explained with reference to FIGS. 4A to 4D.
First, as shown in FIG. 4A, the semiconductor substrate 1 having the integrated circuit 2, the electrodes 3, and the passivation film 4 is provided. The description of the semiconductor substrate 1 shown in FIGS. 4A to 4D is omitted since it is similar to the semiconductor substrate 1 shown in FIG. 3A.
Next, as shown in FIG. 4B, the lower wiring layer 21 is formed on the passivation film 4 above the semiconductor substrate 1. The lower wiring layer 21 includes an interconnecting conductive layer 26 connected to the electrodes 3 and the spiral coil 24. The spiral coil 24 is to be connected to the interconnecting conductive layer 26 and the electrodes 3 in a later stage.
The material of the lower wiring layer 21 may be, aluminum or copper, for example, and the thickness of thereof may be between 0.1 μm and 10 μm, for example. The lower wiring layer 21 may be formed using any well-known method, for example, sputtering, evaporation, plating, or the like.
Next, as shown in FIG. 4C, the insulating resin layer 22 is formed over the passivation film 4 and the lower wiring layer 21 above the semiconductor substrate 1. The insulating resin layer 22 may be made of, for example, a polyimide resin, an epoxy resin, a silicone resin, or the like, and the thickness thereof may be between0.1 μm and 10 μm, for example. The insulating resin layer 22 may be formed using any well-known method, for example, the spin coating method, the printing method, the lamination method, or the like. In the insulating resin layer 22, the openings 25 are defined in the positions corresponding to the interconnecting conductive layer 26 and ends 24a of the spiral coil 24 (two openings are shown in FIGS. 4C and 4D). The openings 25 may be defined using a patterning technique or the like, by means of photolithography, for example.
Next, as shown FIG. 4D, the upper wiring layer 23 is formed on the insulating resin layer 22. The two ends 23a and 23b of the upper wiring layer 23 penetrate through the openings 25 defined in the insulating resin layer 22, and are connected to the interconnecting conductive layer 26 and the ends 24a of the spiral coil 24, respectively. In this manner, the spiral coil 24 is connected to the electrodes 3 via the upper wiring layer 23 (over path) and the interconnecting conductive layer 26.
The material of the upper wiring layer 23 may be, for example, copper, and the thickness thereof may be, for example, between 1 μm and 20 μm. The upper wiring layer 23 may be formed, for example, using any well-known technique, such as electroplating.
However, the conventional semiconductor device 20 as shown in FIGS. 3A to 3D and FIGS. 4A to 4D still have shortcomings as follows.
Referring to FIG.5, an equivalent circuit of the conventional semiconductor device is shown. In FIG.5, Csis the capacitance of the spiral coil, Rsis the electrical resistance of the spiral coil, and Ls is the inductance of the spiral coil. C(ox+Resin) is the capacitance of the passivation film and the insulating resin layer, Csi is the capacitance of the semiconductor substrate (silicon substrate), and Rsi is the electrical resistance of the semiconductor substrate (silicon substrate).
Provision of the spiral coil 24 on the upper wiring layer 23 as shown in FIGS. 3A to 3D suffers from the following shortcomings (1) and (2).
(1) Because the lower wiring layer 21 and the semiconductor substrate 1 are close, CSi is increased due to parasitic capacitance, which results in energy loss.
(2) Because the lower wiring layer 21 and the upper wiring layer 23 (the spiral coil 24) are close, CS is increased, causing energy loss.
Provision of the spiral coil 24 on the lower wiring layer 21 as shown in FIGS. 4A to 4D suffers from the following shortcomings (1) and (2).
(1) Because the lower wiring layer 24 and the semiconductor substrate 1 are close, RSi is increased due to eddy current loss, which results in energy loss.
(2) Because the lower wiring layer 21 and the upper wiring layer 23 (the spiral coil 24) are close, CS is increased, causing energy loss.
As described previously, in recent years, in a fabrication of a high-frequency semiconductor element, an induction element, such as a spiral inductor, is formed on a semiconductor substrate for the purpose of ensuring impedance matching thereof or the like (see, for example, Japanese Unexamined Patent Application, First Publication No. 2003-86690). Therefore, one technique is proposed in which a thick resin layer is provided between the semiconductor substrate and the induction element so that loss of electromagnetic energy is reduced.
In a conventional semiconductor device, however, a multi-layered wiring structure may be required. In such a case, impedance mismatching occurs at the junctions (contact holes) that connect an induction element and a wiring that are formed in the different layers, which may result in a decrease in the quality factor value (Q value).